The internet-of-things (IoT) is how the networking sensors are placed on everyday physical objects to perform meaningful sensing and communication. Since its conception, IoT has been touted as the next wave of computing with exponential growth prospects however this growth outlook has been tempered by technological challenges. Ideally, IoT devices should be seamlessly deployed without the need for maintenance through technology such as battery-less devices that run on harvested energy. IoT edge-devices have to address the modern computing needs of machine-learning and deep-learning to have a dedicated computing infrastructure for even higher power gains.
Power efficiency and effective use of available spectrum by IoT devices are two core issues being addressed. A typical approach is to make more energy available for the system through efficient and Ultra-low-power (ULP) energy harvesting while also reducing the power consumption of existing circuits and system architecture to overcome the energy gap. The latest ULP design techniques are leading to an overhaul of existing circuit and system architectures.
Technology Overview
Northeastern researchers developed an analog computing infrastructure with new highly precise amplifiers achieving stabilities down to 10s of ppm/degree to realize, ultra-low power, and lower area multiplier, adder, and other arithmetic circuits. An analog computing method includes generating a biasing current (IWi) using a constant gm bias circuit operating in the sub threshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). 
This method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.
- Enables ultra-low power analog computing
- Significantly reduces the size and power consumption of a machine learning ASIC 
- Lowers energy output/energy requirements for devices 
- Cuts down the testing cost 
- Developing machine-learning, deep-learning, analog computing hardware
- Foundational blocks for developing on-chip analog multiplier, convolutional blocks, etc. needed for the machine learning algorithm
- Computer vision, speech recognition, and processing, feature extraction are the application of ASIC
- License
- Partnering
- Research collaboration
Patent Information:
Deep Learning
For Information, Contact:
Mark Saulich
Associate Director of Commercialization
Northeastern University
Aatmesh Shrivastava